False-colour scanning electron micrograph of the surface of a 7401 TTL integrated circuit, showing arrangement of component metal oxide silicon (MOS) transistors in patterned layers (top & centre) & bonding pad of a single connecting lead (bottom). MOS transistors are manufactured by oxidising an original silicon wafer to give a layer of silicon oxide (SiO2). This is coated with a photoresist & exposed to light through a mask (so as to produce the pattern). Unmasked areas become etchable & are removed, together with underlying SiO2 layer. The masked wafer is then doped with n-type and then p- type impurities in a furnace. Magnification: x150 at 6x4.5cm size, x100 at 35mm size. Chip is a Quad 2 Input NAND gate, open collector output. NAND denotes a 2 input logic gate; the.
Model release not required. Property release not required.