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False-col SEM of integrated circuit

False-col SEM of integrated circuit

T370/0468

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Credit

DR JEREMY BURGESS / SCIENCE PHOTO LIBRARY. DR JEREMY BURGESS / SCIENCE PHOTO LIBRARY.

Caption

False colour scanning electron micrograph (SEM) of the surface of a 7401 TTL integrated circuit, showing arrangement of component metal oxide silicon (MOS) transistors in patterned layers. MOS transistors are manufactured by oxidising an original silicon wafer to give a layer of silicon oxide (Si02). This is coated with a photoresist & exposed to light through a mask (ie to produce pattern). Unmasked areas become etchable & are removed, together with underlying SiO2 layer. The masked wafer is then doped with n-type and then p- type impurities in a furnace. Magnification: X 320 at 10x8 inch size, X45 at 35mm size. Chip is a Quad 2 Input NAND gate, open collector output. NAND denotes a 2 input logic gate; the output is one if and only if both inputs are zero;.

Release details

Model release not required. Property release not required.

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