DR JEREMY BURGESS / SCIENCE PHOTO LIBRARY DR JEREMY BURGESS / SCIENCE PHOTO LIBRARY
Coloured scanning electron micrograph of the surface of a 7401 TTL integrated circuit (IC) (TTL denotes transistor-transistor logic). The image shows the whole chip attached to its ceramic substrate (the upper ceramic layer has been removed to reveal chip itself), with 14 connecting leads bonded around the periphery of the chip. Since 2 of these leads are connections for common & ground, it may be assumed that the chip contains at least 12 transistors. The image also reveals the arrangement of the MOS (metal oxide silicon) transistors in patterned layers, etched onto surface of the original silicon wafer. Magnification: x30 at 6x4.5cm size. Chip is a Quad 2 Input NAND gate, open collector.
Model release not required. Property release not required.